Responsible for Physical Verification, Reliability Sign-off, EM/IR Analysis, Power Grid Design, Analog/Mixed-Signal Integration, and methodology development for complex low-power SoCs targeting IoT and MCU applications Your role Key responsibilities in your new role - Drive **Physical Verification (PV), ESD, and Reliability Sign-off** activities for complex low-power SoCs targeting IoT and MCU applications. - Perform **Physical Design and Timing Closure** for ICW SoCs. Execute and own **Physical Verification and Reliability Checks** to ensure design quality and manufacturability. - Conduct **Power Grid Design**, including power switch estimation and optimization. - Perform **Static and Dynamic EM/IR Analysis** for multi-voltage and multi-power domain designs. - Lead **I/O Planning and Package Co-design** activities for SoC implementation. - Drive **Analog and Mixed-Signal IP Integration** into SoC designs. - Develop and improve **design flows, methodologies, QoR (Quality of Results), and sign-off processes**. - Collaborate closely with **Physical Design, STA, DFT, RTL, DV Engineers, and Chip Architects** to ensure successful project execution. - Support implementation of SoCs with **multiple voltage islands, power islands, and low-power design techniques** Your profile Qualifications and skills to help you succeed - Bachelor’s or Master’s degree in **VLSI Design** with 5 -8 years of relevant industry experience. - Hands-on experience in **Physical Verification (PV), ESD, and Reliability Sign-off** for complex SoCs. - Strong expertise in **Power Grid Design**, Power Switch Estimation, and **Static/Dynamic EMIR Analysis** for multi-voltage and multi-power domain designs. - Deep understanding of **low-power SoC implementation**, including multiple voltage islands, power islands, and power reduction techniques. - Experience with industry-standard **Physical Verification and Power Grid Sign-off tools**. - Knowledge of semiconductor technologies including **40nm, 28nm, and 22nm nodes**, along with **WireBond and FlipChip packaging** methodologies. - Proficiency in scripting and automation using **Shell, Perl, Tcl**, and Make-based flows. - Experience in **I/O Planning, Package Co-design**, and **Analog/Mixed Signal IP Integration** for SoC designs. - Proven ability to drive **flow and methodology improvements** to enhance QoR and Sign-off efficiency. - Strong ownership, technical commitment, and a results-oriented mindset. - Highly organized, detail-oriented, and methodical in problem-solving and execution. - Demonstrated ability to take initiative, drive innovation, and overcome technical challenges. - Effective collaborator with the ability to work across **Physical Design, STA, DFT, RTL, DV, and Architecture teams**. - Excellent communication skills with a track record of knowledge sharing and cross-functional partnership #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various [contact channels](https://www.infineon.com/cms/en/about-infineon/company/contacts/) and about [Diversity & Inclusion](https://www.infineon.com/cms/en/careers/diversity-and-inclusion/) at Infineon. Keerthini M H